Playground · Systolic array visualizer
Watch a GEMM flow through the NPU.
The GRX930's NPU is an 8×8 weight-stationary systolic array. Weights from B sit still in the grid,
a row of A flows in from the left, skewed one row per step, and partial sums flow down each column into C.
Model Dataflow model of c930_systolic_array.sv and the loop order in c930_npu_core.sv: N tiles, then K tiles, then rows of A. One step here is one hop of the wavefront; the RTL's half-rate hops, weight settle and registered feed are not shown.
Systolic array
- weight from B (stationary)
- activation from A, this step
- partial sum, this step
A
B
C = A × B
Sources: c930_systolic_array.sv, c930_npu_core.sv. Limits are the SoC build's: M ≤ 8, N ≤ 12, K ≤ 16. Next: program the same GEMM from the NPU's registers →