Sim-ready infrastructure
Every core ships with Verilator and Icarus Verilog testbenches. Trace data through the photonic accelerator without a physical board.
[ Gridworkz Hardware Core v1.0.0-beta ]Open Silicon.
Open Silicon.
No NDAs.
No Licensing Fees.
Gridworkz is building the Linux of chip design: synthesizable RISC-V64 cores, dual NPUs and a co-packaged photonic tensor accelerator, all open source on GitHub. Built for university labs and research teams.
- Apache 2.0
- Verilator
- OpenLane
- LLVM
- PyTorch
# 1. Clone the complete heterogeneous hardware stack
$ git clone https://github.com/gridworkz/gridworkz-core.git
# 2. Move into the simulation target
$ cd gridworkz-core
# 3. Build and run the photonic matmul demo
$ make sim TARGET=verilator WORKLOAD=photonic_matmul_64
[gridworkz] 'make sim' is not available yet.
[gridworkz] RTL + sim targets are being published in stages.
[gridworkz] Watch the repo for the first release.
Illustrative waveform
Zero-cost deploymentFrom git clone to waveform
Simulate instantly Compile effortlessly Synthesize out of the box
From git clone to waveform
in 10 minutes.
No proprietary licenses. No enterprise contracts. Everything runs on open-source toolchains, on your laptop.
Native compiler support
Drop C/C++ or PyTorch models into the pre-configured LLVM / RISC-V toolchain and watch the NPUs split the work.
FPGA deployment
Verified constraint files and bitstream scripts for standard FPGA dev boards, mirroring the ASIC layout.
Architecture
Every block, exposed.
Select a block to see the Verilog behind it, its register map and its pinout.
GRIDWORKZ DEV PLATFORM
Select a block to view source, registers and pinout →
The open stackLayer 0 · Base Layer 1 · Acceleration Layer 2 · Frontier Layer 3 · Software
Layered like an operating system.
Unhindered bare-metal compute.
A transparent quad-core 64-bit RISC-V block. Modify extensions, design your own instructions and compile with standard LLVM on verified RTL.
Accessible tensor workloads.
Open NPU and GPU designs that expose every register: build custom quantization schemes, study sparsity and change compiler backends.
Co-packaged light-speed compute.
The G100 drives an integrated photonic tensor chiplet for electro-optic co-design and laser-driven analog matrix multiplication.
Programmable hardware. Zero assembly required.
Write parallel C++ with the open, LLVM-backed GCA SDK. If you can write CUDA or HIP, you can write kernels for Gridworkz.
__global__ void vectorAdd(float* A, float* B, float* C, int N) {
int i = gca_blockIdx_x * gca_blockDim_x + gca_threadIdx_x;
if (i < N) C[i] = A[i] + B[i];
}For labs
Request an evaluation board for your lab.
Ready to move from simulation to physical hardware? We supply FPGA evaluation kits to qualified university labs and public research teams.
Stop buying black boxes.
Start building the future of hardware.
Fork the codebase, simulate with Verilator or OpenLane, or order a board to test your ideas on real silicon.