Real runs, not descriptions of them.

[PASS] GEMM M=3 N=10 K=13 verified
[TEST] random M=7 N=8 K=4 (seed 2013)
[PASS] GEMM M=7 N=8 K=4 verified
[TEST] random M=7 N=8 K=13 (seed 2014)
[PASS] GEMM M=7 N=8 K=13 verified
[TEST] random M=6 N=3 K=14 (seed 2015)
[PASS] GEMM M=6 N=3 K=14 verified
[PTA] the register block at 0x100
[PTA]   [PASS] PTA_ID, and CAPS c0802008 00000200 00020000, read-only
[PTA]   [PASS] the decode, and 0x00-0x3C untouched
[PTA]   [PASS] MODEL_RST clears the correction
[PTA]   [PASS] SHOT_CT +0, WLOAD_CT +2, C exact at 16
  [DMA] WATCHDOG TIMEOUT: core did not respond within 2048 cycles
[PTA]   [PASS] MZM_NL refused, and the next valid start cleared it
  [DMA] WATCHDOG TIMEOUT: core did not respond within 2048 cycles
  [DMA] WATCHDOG TIMEOUT: core did not respond within 2048 cycles
  [DMA] WATCHDOG TIMEOUT: core did not respond within 2048 cycles
  [DMA] WATCHDOG TIMEOUT: core did not respond within 2048 cycles
  [DMA] WATCHDOG TIMEOUT: core did not respond within 2048 cycles
  [DMA] WATCHDOG TIMEOUT: core did not respond within 2048 cycles
  [DMA] WATCHDOG TIMEOUT: core did not respond within 2048 cycles
[PTA]   [PASS] CAPS1 0000000 agrees with the starts: 7 of 7 refused
[PASS] all NPU tests passed
tb/tb_c930_npu.sv:969: $finish called at 480345 (1s)

  GEMM INT8   2x 3x 5  PASS
  GEMM INT8   4x 4x 4  PASS
  GEMM INT8   5x 7x 9  PASS
  GEMM INT8   8x 1x 4  PASS
  GEMM INT8   8x 4x 1  PASS
  GEMM INT8   8x12x16  PASS
  GEMM INT8   3x 9x11  PASS
  GEMM INT16  4x 4x 4  PASS
  GEMM FP16   4x 4x 4  PASS
  GEMM BF16   4x 4x 4  PASS
  GEMM INT4   4x 4x 4  PASS
  GEMM INT16  2x 3x 5  PASS
  GEMM FP16   2x 3x 5  PASS
  GEMM BF16   2x 3x 5  PASS
  GEMM INT4   2x 3x 5  PASS
Float across K tiles:
  GEMM FP16   5x 7x 9  PASS
  GEMM BF16   5x 7x 9  PASS
  GEMM FP16   3x 9x11  PASS
  GEMM BF16   3x 9x11  PASS
  GEMM FP16   8x12x16  PASS
  GEMM BF16   8x12x16  PASS
  total 24/24
tb/tb_npu_float_prec.sv:412: $finish called at 184425 (1s)

../rv64imac/RTL/riscv_core_csr_unit.sv:304: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
../rv64imac/RTL/riscv_core_csr_unit.sv:304: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
../rv64imac/RTL/riscv_core_csr_unit.sv:304: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
../rv64imac/RTL/riscv_core_csr_unit.sv:304: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
../rv64imac/RTL/riscv_core_csr_unit.sv:304: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
../rv64imac/RTL/riscv_core_csr_unit.sv:304: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
../rv64imac/RTL/riscv_core_csr_unit.sv:304: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
../rv64imac/RTL/riscv_core_csr_unit.sv:304: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
../rv64imac/RTL/riscv_core_top.sv:1987: warning: Instantiating module riscv_core_hazard_unit with dangling input port 17 (i_hazard_unit_illegal_instr) floating.
../rv64imac/RTL/riscv_core_top.sv:1297: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
tb/tb_hazard_csrflush.sv:28: warning: Instantiating module riscv_core_hazard_unit with dangling input port 10 (i_hazard_unit_pc_id) floating.
tb/tb_hazard_csrflush.sv:28: warning: Instantiating module riscv_core_hazard_unit with dangling input port 11 (i_hazard_unit_pc_ex) floating.
../rv64imac/RTL/riscv_core_compressed_decoder.sv:40: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
../rv64imac/RTL/riscv_core_compressed_decoder.sv:42: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
../rv64imac/RTL/riscv_core_compressed_decoder.sv:123: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
../rv64imac/RTL/riscv_core_compressed_decoder.sv:183: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
../rv64imac/RTL/riscv_core_compressed_decoder.sv:232: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
../rv64imac/RTL/riscv_core_compressed_decoder.sv:289: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
../rv64imac/RTL/riscv_core_compressed_decoder.sv:372: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
../rv64imac/RTL/riscv_core_dcache_memory.sv:103: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
../rv64imac/RTL/riscv_core_dcache_memory.sv:164: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
vvp build/tb_hazard_csrflush.vvp
[PASS] hazard CSR-flush deferral + CSR-read stall checks passed
tb/tb_hazard_csrflush.sv:239: $finish called at 240 (1s)

../rv64imac/RTL/riscv_core_csr_unit.sv:304: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
../rv64imac/RTL/riscv_core_csr_unit.sv:304: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
../rv64imac/RTL/riscv_core_csr_unit.sv:304: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
../rv64imac/RTL/riscv_core_csr_unit.sv:304: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
../rv64imac/RTL/riscv_core_csr_unit.sv:304: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
../rv64imac/RTL/riscv_core_csr_unit.sv:304: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
../rv64imac/RTL/riscv_core_csr_unit.sv:304: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
../rv64imac/RTL/riscv_core_csr_unit.sv:304: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
../rv64imac/RTL/riscv_core_csr_unit.sv:304: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
../rv64imac/RTL/riscv_core_csr_unit.sv:304: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
../rv64imac/RTL/riscv_core_top.sv:1987: warning: Instantiating module riscv_core_hazard_unit with dangling input port 17 (i_hazard_unit_illegal_instr) floating.
../rv64imac/RTL/riscv_core_top.sv:1297: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
../rv64imac/RTL/riscv_core_compressed_decoder.sv:40: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
../rv64imac/RTL/riscv_core_compressed_decoder.sv:42: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
../rv64imac/RTL/riscv_core_compressed_decoder.sv:123: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
../rv64imac/RTL/riscv_core_compressed_decoder.sv:183: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
../rv64imac/RTL/riscv_core_compressed_decoder.sv:232: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
../rv64imac/RTL/riscv_core_compressed_decoder.sv:289: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
../rv64imac/RTL/riscv_core_compressed_decoder.sv:372: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
../rv64imac/RTL/riscv_core_dcache_memory.sv:103: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
../rv64imac/RTL/riscv_core_dcache_memory.sv:164: vvp.tgt sorry: Case unique/unique0 qualities are ignored.
vvp build/tb_hazard_equiv.vvp
[PASS] tb_hazard_equiv: 300000 cycles, 1095 forward-active cycles, all outputs bit-equal
tb/tb_hazard_equiv.sv:279: $finish called at 3000050 (1s)

iverilog -g2012 -Wall -I rtl/pta -o build/tb_arb_bskid_equiv.vvp rtl/c930_axi_dma_arb.sv tb/c930_axi_dma_arb_ref.sv tb/tb_arb_bskid_equiv.sv
tb/tb_arb_bskid_equiv.sv:429: warning: Static variable initialization requires explicit lifetime in this context.
tb/tb_arb_bskid_equiv.sv:430: warning: Static variable initialization requires explicit lifetime in this context.
tb/tb_arb_bskid_equiv.sv:487: warning: Static variable initialization requires explicit lifetime in this context.
tb/tb_arb_bskid_equiv.sv:490: warning: Static variable initialization requires explicit lifetime in this context.
tb/tb_arb_bskid_equiv.sv:491: warning: Static variable initialization requires explicit lifetime in this context.
warning: Some design elements have no explicit time unit and/or
       : time precision. This may cause confusing timing results.
       : Affected design elements are:
       :   -- module c930_axi_dma_arb declared here: rtl/c930_axi_dma_arb.sv:17
       :   -- module c930_axi_dma_arb_ref declared here: tb/c930_axi_dma_arb_ref.sv:17
vvp build/tb_arb_bskid_equiv.vvp
[PASS-strict] 1200 txns, both units 1200 B/master, order+payload exact
[INFO] aw_txns=1200 ref: aw=4014 B=4014 | dut: aw=4023 B=4023
[INFO] completeness (withdrawal-affected): DUT 4023/4023 B/AW, REF 4014/4014
[PASS] tb_arb_bskid_equiv: strict DUT completeness exact, random-mode common-prefix order+payload exact vs pristine ref       1200
tb/tb_arb_bskid_equiv.sv:508: $finish called at 1504875000 (1ps)

ROOT      /home/runner/work/grx930/grx930
IVERILOG  Icarus Verilog version 12.0 (stable) ()
LOGS      /home/runner/work/grx930/grx930/c930/build/real_work/<workload>.log

WORK l2-coherent: PASS (ALL L2 TESTS PASSED; $finish called at 2055000 (1ps); 0s, model 117 KB)
WORK ar-withdraw: PASS (ALL AR/AW-WITHDRAW TESTS PASSED (180 checks); $finish called at 5115000 (1ps); 0s, model 274 KB)
WORK quad-four-core: PASS (QUAD-ISOLATED TEST PASSED; all four cores verified their C matrices on-core; TB readback: all 50 C elements across 4 GEMMs correct; $finish called at 88905000 (1ps); 10s, model 13 MB)
REAL WORK: PASS -- 3 finished, 0 failed, 0 blocked (of 3 run, 10s of build and simulation)
SUMMARY   /home/runner/work/grx930/grx930/c930/build/real_work/real_work_summary.md